package ygo

import (  "fmt"
	  "dumpwave"
)

func dmux(
		decodeDmux	chan DEDM,
		registerDmux	chan REDM,
		dmuxAlu		chan DMAL) {
	for{
		dedm :=<- decodeDmux
		switch dedm.DMUX_UNIT{
			case ALU:
				switch dedm.DMUX_COMMAND{
					case RRS_RRT_WRD:
						fmt.Println("[DMUX] DEDM <-- DECODE (unit: ALU, cmd: RRS_RRT_WRD)")

						redm :=<- registerDmux
						fmt.Println("[DMUX] REDM <-- REGISTER (bus1: , bus2: )")

						fmt.Println("[DMUX] DMAL --> ALU (bus1: , bus2: )")
						dmuxAlu <- DMAL{BUS1:redm.BUS1, BUS2:redm.BUS2}

					case RRS_WRT:
						fmt.Println("[DMUX] DEDM <-- DECODE (unit: ALU, cmd: RRS_WRT)")

						redm :=<- registerDmux
						fmt.Println("[DMUX] REDM <-- REGISTER (bus1: , bus2: )")

						fmt.Println("[DMUX] DMAL --> ALU (bus1: , bus2: )")
						dmuxAlu <- DMAL{BUS1:redm.BUS1, BUS2:redm.BUS2}

					case RRS_RRT:
						fmt.Println("[DMUX] DEDM <-- DECODE (unit: ALU, cmd: RRS_RRT)")
						
						redm :=<- registerDmux
						fmt.Println("[DMUX] REDM <-- REGISTER (bus1: , bus2: )")

						fmt.Println("[DMUX] DMAL --> ALU (bus1: , bus2: )")
						dumpwave.Wave(1,"req_ack_DEDM")
						dumpwave.Wave(int(redm.BUS1),"cha_DEDM")
						dmuxAlu <- DMAL{BUS1:redm.BUS1, BUS2:redm.BUS2}
						dumpwave.Wave(0,"req_ack_DEDM")
				}
		}
	}
}
